Role: VLSI Physical Designer
Domain: VLSI / Semiconductor
Experience: 6–9 Years
Notice Period: Immediate to 15 Days
Location: Anywhere in the USA / Remote
Technical Skills Required: Physical Design & RTL-to-GDSII
- RTL synthesis, placement, and routing using Synopsys Fusion Compiler
- Block and SoC floorplanning
- Clock Tree Synthesis (CTS)
- Timing, power, area, and design-rule optimization
- Static Timing Analysis (STA) using PrimeTime
- Parasitic extraction using StarRC
- EM/IR closure using RedHawk-SC
- Physical verification using Siemens Calibre, including DRC, LVS, antenna, and density checks
- Experience with advanced technology nodes such as 5nm and 3nm
- Logical ECOs using Formality ECO
- Timing ECOs using PrimeClosure
- 6–9 years of hands-on VLSI Physical Design experience
- Strong expertise in Synopsys physical design and signoff tools
- Experience with RTL-to-GDSII implementation and timing closure
- Immediate joiners or candidates with a maximum 15-day notice period preferred
Rate:
Not specified
Location:
United Kingdom
IR35 Status:
Outside
Remote Status:
Remote
Industry:
Engineering
Seniority Level:
Senior