VLSI CAD Engineer
Posted 2 days ago by Tech Observer
Negotiable
Undetermined
Remote
Remote
Summary: The Senior VLSI CAD Engineer role focuses on VLSI chip development and semiconductor technology, requiring expertise in Cadence design automation and layout verification tools. Candidates should possess a strong background in electrical or computer engineering and have significant experience with relevant programming languages and tools. The position is remote and offers a contract duration of 6 to 12 months, with potential for extension.
Key Responsibilities:
- Develop and maintain Cadence design automation infrastructure.
- Utilize Cadence SKILL programming language and related languages for VLSI chip development.
- Perform layout verification using tools such as Cadence Pegasus, Synopsys ICV, or Siemens Calibre.
- Debug errors and solve problems collaboratively within a team environment.
- Work with Linux environments and shell scripting.
Key Skills:
- Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Physics Engineering, or related field.
- Experience in VLSI chip development or semiconductor technology.
- Proficiency in Cadence design automation tools and scripting (SKILL, Python, Perl).
- Strong understanding of physical layout and technology ground rules.
- Experience with version control systems like Git.
Salary (Rate): £37.50 hourly
City: undetermined
Country: undetermined
Working Arrangements: remote
IR35 Status: undetermined
Seniority Level: undetermined
Industry: IT
Detailed Description From Employer:
Job Title: Senior VLSI CAD Engineer
Location: Remote
Duration: 6- 12 months (with possible extension)
Job Description:
Required professional and technical expertise:
Bachelor or above Degree in Electrical Engineering, Computer Engineering, Physics Engineering or related field with experience in VLSI chip development or semiconductor technology
Experiences with Cadence design automation infrastructure development (SKILL, Python or Perl scripting)
Experiences with Cadence SKILL programming language and/or related languages (Python and/or Perl, etc), at least 3 years.
Familiarity with layout verification tools from Cadence Pegasus, Synopsys ICV, or Siemens Calibre, including design rule checking (DRC) with 3+ years of relevant experience
Strong understanding of Linux environments and shell scripting with a minimum of 2+ years of experience
Strong understanding of physical layout and technology ground rules
Ability to debug errors and solve problems in a team environment
Preferred Professional and technical expertise:
Strong experience using the Cadence Virtuoso layout design tool, at least 5 years
Experiences with Cadence SKILL programming language for Pcell Development & Design Automation, at least 3 years
Experience with Cadence Virtuoso automated layout design tools, at least 2 years
Experience with Cadence techfile/mapfile creation or updates is a great plus
Experience with version control systems such as Git and familiarity with collaborative software development workflows (e.g., GitHub, GitLab, or Bitbucket)
Experienced user of Synopsys ICV DRC checking tool
Experience with advanced sub-micron semiconductor technology nodes