Static Timing Analysis (STA) Engineer

Static Timing Analysis (STA) Engineer

Posted 1 week ago by 1753171093

Negotiable
Outside
Remote
USA

Summary: The Senior ASIC Engineer, specializing in Static Timing Analysis, is responsible for developing complex timing constraints compatible with RTL and signoff. The role involves driving pre-route timing checks, maintaining RTL quality metrics, and executing custom regression scripts for complex designs. Candidates should possess a strong mix of SDC knowledge, EDA tool competence, and TCL scripting capabilities. The position offers remote work options or locations in San Jose, Austin, or Longmont, with a contract duration of over 12 months.

Key Responsibilities:

  • Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
  • Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
  • Requires a mix of SDC knowledge, EDA tool competence and TCL based scripting capability (in both EDA environment and standalone Linux TCL shell scripts)
  • Constantly review/identify the places to improve the process and ways to identify the issues early in the design phase.
  • Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.
  • Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions)
  • Understand the Primetime/Design Compiler checks and review the reports to help clean up in order to meet each milestone targets.
  • Summarize the regression results periodically to track the progress.

Key Skills:

  • Minimum of 6-8 years' experience
  • Worked with EDA tools that enable RTL quality checks
  • Experience with analyzing the timing reports and identifying both the design and constraints related issues.
  • Ability to multitask, ramp up quickly on new flows/tools/ideas.
  • Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable

Salary (Rate): undetermined

City: undetermined

Country: USA

Working Arrangements: remote

IR35 Status: outside IR35

Seniority Level: undetermined

Industry: IT

Detailed Description From Employer:

Role Title: Senior ASIC Engineer, Static Timing Analysis

Location: Remote is an option for right fit / San Jose, CA / Austin, TX / Longmont, CO

Duration: 12+ months contract

Description:

  • Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
  • Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
  • Requires a mix of SDC knowledge, EDA tool competence and TCL based scripting capability (in both EDA environment and standalone Linux TCL shell scripts)
  • Constantly review/identify the places to improve the process and ways to identify the issues early in the design phase.
  • Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.
  • Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions)
  • Understand the Primetime/Design Compiler checks and review the reports to help clean up in order to meet each milestone targets.
  • Summarize the regression results periodically to track the progress.

Preferred Experience:

  • Minimum of 6-8 years' experience
  • Worked with EDA tools that enable RTL quality checks
  • Experience with analyzing the timing reports and identifying both the design and constraints related issues.
  • Ability to multitask, ramp up quickly on new flows/tools/ideas.
  • Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable