silicon verification engineer

Summary: A Silicon Verification Engineer is required for a leading American technology company, focusing on high-speed interface validation. The role is fully remote and requires expertise in SystemVerilog, UVM, and mixed-signal design verification, with a minimum of 2 years of experience. The position is classified as outside IR35.

Key Responsibilities:

• Contribute to high-speed interface validation.
• Utilize SystemVerilog and UVM for design verification.
• Engage in mixed-signal design verification tasks.

Key Skills:

• 2+ years of experience in Silicon Verification.
• Proficiency in SystemVerilog.
• Experience with UVM.
• Knowledge of mixed-signal design verification.

Salary (Rate): £30.00 hourly

City: Redmond

Country: United States

Working Arrangements: remote

IR35 Status: outside IR35

Seniority Level: undetermined

Industry: IT