Senior Asic Rtl Design

Summary

REMOTE OFFSITE: FROM HOME

2 Contract positions interviewing now, for Mid November start dates:

12-18 Months + CONTRACT

SENIOR ASIC RTL Design (need ASIC-RTL Design not FPGA)

Strong Verilog

High Speed Memory Interface Experience

AXI bus

Multiclock Domain Designs

Logic synthesis & Timing constraints

Forward Error Correction (FEC), Bit Rate Error (BER) calculations

Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation

Plusses:

1. LPDDR5

2. UFS/Flas.1

3. PCIe Gen3/4/5