Post Silicon NPU Validation Engineer

Summary: The PSV NPU Validation Engineer role involves developing and executing validation test plans for NPUs, collaborating with cross-functional teams, and optimizing validation methodologies. The position requires a strong background in system validation, debugging, and characterization of complex systems, particularly in the context of silicon bring-up and SoC-level IPs. Candidates should possess extensive experience in relevant technologies and programming skills to support automation and testing efforts. This role is remote and classified as outside IR35.

Key Responsibilities:

• Develop end-to-end system validation test plans for the NPU, including characterization.
• Collaborate with cross-functional teams, including software and hardware engineers, to design optimal test validation and characterization solutions.
• Create, modify, and refine tests based on a deep understanding of the NPU design, ensuring comprehensive coverage and suggesting improvements where necessary.
• Lead the development and execution of bring-up, validation, qualification, tuning, and productization plans.
• Build and integrate necessary tools, scripts, and infrastructure in close collaboration with stakeholders.
• Spearhead post-silicon bring-up efforts and provide expert support for debugging activities.
• Drive continuous optimization of validation and productization methodologies to improve overall process efficiency and quality.

Key Skills:

• B.E/M. E in Electronics & Communication Engineering.
• 5 to 8 years of experience.
• Minimum 6 years of experience in validating and debugging complex systems.
• In-depth knowledge of computing architecture, technical debugging, and validation strategies.
• Hands-on experience with silicon bring-up, debugging, and characterization of SoC-level IPs (e.g., PCIe Gen 4/5, LPDDR4/5, PLL/DLL, NOR Flash, SPI, I2C, RISC-V processors), with familiarity in memory and I/O interfaces.
• Strong debugging skills with the ability to analyze complex issues using first principles.
• Experience with Lauterbach Debugger for RISC-V and lab equipment (oscilloscopes, BERT, power supplies, logic analyzers) is strongly preferred.
• Solid foundation in digital design, microarchitecture, timing, power, noise, control systems, and HW/SW interaction, including firmware.
• Proficiency in programming/scripting (C/C++, Perl, Ruby, Python) for automation, test scripting, and GUI development. Knowledge of signal and power integrity is a plus.

Salary (Rate): undetermined

City: undetermined

Country: USA

Working Arrangements: remote

IR35 Status: outside IR35

Seniority Level: undetermined

Industry: IT