LLM Trainer ASIC/VLSI Design (Chip Lead)

LLM Trainer ASIC/VLSI Design (Chip Lead)

Posted 1 week ago by 1754714447

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Negotiable
Outside
Remote
USA
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Artificial Intelligence Automation Nodes (Networking) State Children's Health Insurance Programs Verification And Validation Workflows Written English

Summary: The role of LLM Trainer ASIC/VLSI Design (Chip Lead) involves training and evaluating Large Language Models specifically for chip design workflows. The position requires a senior ASIC/VLSI design expert to create datasets, simulate engineering scenarios, and review AI outputs to enhance accuracy in the semiconductor field. This is a remote contract position focused on improving design processes through AI integration. The ideal candidate will have extensive experience in ASIC/VLSI design and a strong understanding of ARM-based SoC design.

Key Responsibilities:

  • Create datasets covering ASIC/SoC workflows (RTL, verification, physical design).
  • Simulate realistic prompts/conversations involving chip design tools and issues.
  • Write and review technical explanations for ARM-based SoC design, tape-out, and optimization.
  • Evaluate and refine model responses for accuracy and clarity.
  • Cover full lifecycle from design specs to GDSII signoff (<45nm nodes, TSMC/UMC/GlobalFoundries).

Key Skills:

  • 8+ years in ASIC/VLSI design; end-to-end IC design leadership with multiple successful tape-outs.
  • Expertise in RTL (Verilog/VHDL/SystemVerilog), synthesis, timing closure, DFT/DFM, SoC architecture.
  • Direct experience with ARM processor integration.
  • Strong written English for explaining complex workflows.
  • Comfortable collaborating with AI teams.

Salary (Rate): undetermined

City: undetermined

Country: USA

Working Arrangements: remote

IR35 Status: outside IR35

Seniority Level: Senior

Industry: IT

Detailed Description From Employer:

Position: LLM Trainer ASIC/VLSI Design (Chip Lead)

Location: Remote | Contract

Overview:

Looking for a senior ASIC/VLSI design expert to help train and evaluate Large Language Models for chip design workflows. You will create high-quality datasets, simulate engineering scenarios, and review AI outputs to improve accuracy in the semiconductor domain.

Key Responsibilities:

  • Create datasets covering ASIC/SoC workflows (RTL, verification, physical design).
  • Simulate realistic prompts/conversations involving chip design tools and issues.
  • Write and review technical explanations for ARM-based SoC design, tape-out, and optimization.
  • Evaluate and refine model responses for accuracy and clarity.
  • Cover full lifecycle from design specs to GDSII signoff (<45nm nodes, TSMC/UMC/GlobalFoundries).

Requirements:

  • 8+ years in ASIC/VLSI design; end-to-end IC design leadership with multiple successful tape-outs.
  • Expertise in RTL (Verilog/VHDL/SystemVerilog), synthesis, timing closure, DFT/DFM, SoC architecture.
  • Direct experience with ARM processor integration.
  • Strong written English for explaining complex workflows.
  • Comfortable collaborating with AI teams.

Nice-to-Have:

  • AI/ML tooling exposure, EDA automation, or cloud-based design experience.
  • Technical documentation/training material creation experience.
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