DV Engineers DDR (either IP or SoC level experience)- Remote
Posted 1 week ago by 1753424491
Negotiable
Outside
Remote
USA
Summary: The role of DV Engineers DDR focuses on verification strategies and test plans for DDR memory interface designs, requiring extensive experience in ASIC/IP/SoC verification. The position involves developing UVM/SystemVerilog-based testbenches, performing protocol-level verification, and collaborating with various teams to ensure design compliance. Candidates are expected to lead technical reviews and mentor junior engineers while driving improvements in functional coverage. This is a remote position based in the USA, suitable for individuals with over 10 years of relevant experience.
Key Responsibilities:
- Define and implement verification strategies and test plans for DDR memory interface designs.
- Develop UVM/SystemVerilog-based testbenches and reusable verification components.
- Perform protocol-level verification for DDR memory interfaces and validate compliance.
- Collaborate with architecture, RTL, and system teams to understand design intent and corner cases.
- Own functional coverage, regression setup, and closure.
- Integrate DDR models, controllers, PHYs, and validate their interactions.
- Debug and resolve simulation failures and functional issues.
- Drive code and functional coverage improvements to ensure thorough verification.
- Lead or participate in technical reviews and mentor junior engineers.
Key Skills:
- 10+ years of hands-on experience in ASIC/IP/SoC verification.
- Strong expertise in SystemVerilog, UVM, and functional coverage methodology.
- In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols.
- Experience with DDR controllers, PHY integration, and JEDEC standards.
- Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc.
- Good scripting skills in Python, Perl, or Shell for automation and regression management.
- Excellent debugging and problem-solving skills.
- Familiarity with AXI/AHB protocols and interconnects is a plus.
- Experience working with memory models and timing analysis.
Salary (Rate): undetermined
City: undetermined
Country: USA
Working Arrangements: remote
IR35 Status: outside IR35
Seniority Level: undetermined
Industry: IT
Role: DV Engineers DDR (either IP or SoC level experience)
Work Location: USA (Remote)
Experience: 10+ Years
Key Responsibilities:
Define and implement verification strategies and test plans for DDR memory interface designs.
Develop UVM/SystemVerilog-based testbenches and reusable verification components.
Perform protocol-level verification for DDR memory interfaces and validate compliance.
Collaborate with architecture, RTL, and system teams to understand design intent and corner cases.
Own functional coverage, regression setup, and closure.
Integrate DDR models, controllers, PHYs, and validate their interactions.
Debug and resolve simulation failures and functional issues.
Drive code and functional coverage improvements to ensure thorough verification.
Lead or participate in technical reviews and mentor junior engineers.
Required Skills:
10+ years of hands-on experience in ASIC/IP/SoC verification.
Strong expertise in SystemVerilog, UVM, and functional coverage methodology.
In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols.
Experience with DDR controllers, PHY integration, and JEDEC standards.
Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc.
Good scripting skills in Python, Perl, or Shell for automation and regression management.
Excellent debugging and problem-solving skills.
Familiarity with AXI/AHB protocols and interconnects is a plus.
Experience working with memory models and timing analysis.
Preferred Qualifications:
Experience with post-silicon validation or DDR hardware bring-up.
Knowledge of formal verification tools and techniques.
Experience with low power verification and timing closure tools.
Disclaimer: E-Solutions Inc. provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, gender, sexual orientation, gender identity or expression, national origin, age, disability, genetic information, marital status, amnesty, or status as a covered veteran in accordance with applicable federal, state and local laws. We especially invite women, minorities, veterans, and individuals with disabilities to apply. EEO/AA/M/F/Vet/Disability."
DV Engineers DDR (either IP or SoC level experience)- Remote1DDR,IP or SoC,DV EngineerN/AC2C,W-2,Full Time,Hourly,Contract to Perm,W2United States