DV Engineer/Lead

Summary: The DV Engineer/Lead role involves working on IP/SOC verification with a focus on ARM ecosystems and requires expertise in Verilog, System Verilog, and UVM. The position is remote within the EU and demands a strong background in SOC verification and related technologies. Candidates should possess good communication skills and a willingness to engage fully with the job details.

Key Responsibilities:

• Conduct IP/SOC verification
• Utilize Verilog, System Verilog, and UVM
• Implement code coverage and functional coverage
• Apply SOC verification experience on ARM ecosystem
• Work with PCIE and PCIE-VIP
• Engage in GLS working experience
• Demonstrate proficiency in C/System Verilog and UVM
• Utilize GIT for version control

Key Skills:

• IP/SOC verification
• Verilog, System Verilog, UVM
• Code Coverage, functional coverage
• 5 to 10 years of industry experience
• SOC verification experience on ARM ecosystem
• PCIE experience and PCIE-VIP usage experience
• GLS working experience
• Proficient in C/System Verilog and UVM
• Working knowledge of GIT
• Good communication skills

Salary (Rate): £475.00 Daily

City: London

Country: UK

Working Arrangements: remote

IR35 Status: undetermined

Seniority Level: undetermined

Industry: IT