Position Summary
We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision.
Required Qualifications
- 8+ years of hands-on DFT experience, with significant focus on MBIST.
- Strong experience with Synopsys MBIST (SMS), preferably SMS6 and/or SMS5.
- Proficiency with Synopsys VCS for MBIST verification and simulation.
- Deep understanding of the complete MBIST flow:
- MBIST insertion
- Top-level integration
- Verification
- Pattern generation (Vecgen)
- Diagnostics
- Simulation and debug
- Strong understanding of MBIST test algorithms (e.g., March algorithms) and memory repair schemes (BIRA/BISR, redundancy analysis, spare row/column allocation).
- Experience running and debugging:
- No-delay simulations
- With-delay simulations
- Experience supporting silicon bring-up, post-silicon debug, and root-cause analysis of MBIST and memory-related failures.
- Strong debugging and root-cause analysis skills across RTL, MBIST, and simulation environments.
- Ability to work independently with minimal supervision.
- Experience with large, complex SoC designs containing multiple memory instances.
- Familiarity with Verilog/SystemVerilog and standard DFT methodologies.
Rate:
Not specified
Location:
San Jose
IR35 Status:
Outside
Remote Status:
Remote
Industry:
Engineering
Seniority Level:
Senior