DFT Engineer

Summary: The DFT Engineer role involves overseeing Design for Testability (DFT) aspects of ASIC design, requiring a deep understanding of digital design concepts and methodologies. The position emphasizes collaboration within a team environment and adherence to the Northrop Grumman ASIC development process. Candidates must possess extensive experience in ASIC design and proficiency in relevant coding languages and tools. U.S. citizenship is required for this position.

Key Responsibilities:

• Responsible for DFT (Design for Testability) aspects of ASIC Design with a thorough understanding of digital design concepts.
• Adhere to Northrop Grumman ASIC development process.
• Proficient in VHDL, Verilog or System Verilog RTL coding and DFT methodologies.
• Collaborate across different teams to accomplish project goals.
• Generate test patterns and analyze/debug test failures.
• Work with test engineers to implement ATPG vectors on tester hardware.

Key Skills:

• Bachelor's degree in Electrical or Computer Engineering with 8+ years of experience.
• Experience in full product life cycle of ASIC Design.
• Proficiency in Cadence and/or Mentor test insertion and ATPG tools.
• Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6.
• Experience with memory BIST and logic BIST.
• Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl.
• Effective communication and presentation skills.
• High proficiency in technical problem solving.

Salary (Rate): undetermined

City: undetermined

Country: USA

Working Arrangements: remote

IR35 Status: outside IR35

Seniority Level: undetermined

Industry: IT