Design Verification Engineer

Summary: The Design Verification Engineer/Lead role is a contract position focused on SOC verification, requiring 5 to 10 years of industry experience. The position is remote and open to candidates in the UK and EU countries. Key responsibilities include utilizing PCIE and PCIE-VIP, along with proficiency in C/System Verilog and UVM. Strong communication skills and a willingness to learn are essential for success in this role.

Key Responsibilities:

• Conduct SOC verification.
• Utilize PCIE and PCIE-VIP in verification processes.
• Work with GLS and demonstrate proficiency in C/System Verilog and UVM.
• Manage version control using GIT.
• Communicate effectively and demonstrate a willingness to learn.

Key Skills:

• 5 to 10 years of industry experience.
• SOC verification experience.
• PCIE and PCIE-VIP usage experience.
• Proficient in C/System Verilog and UVM.
• Working knowledge of GIT.
• Good communication skills.
• Willingness to learn.

Salary (Rate): undetermined

City: undetermined

Country: United Kingdom

Working Arrangements: remote

IR35 Status: undetermined

Seniority Level: undetermined

Industry: Other