Design Verification (DV) Engineer

Job Role: Design Verification (DV) Engineer

Location: Remote

Project Duration: 12 – 24 Months

Mandatory Skills

C++, VLSI Design Verification Debug, Software Verification, Verification Framework Development, DevOps, CI/CD Processes & Tools, Good hands-on experience in verification with C or C++.

Senior DV engineers that have substantial experience with C++.

C++ will be used verification (via teal/truss) and not SV/UVM.

Ideally, the candidates would have experience with either DSP and/or Ethernet protocols.