Summary
Overview Contract digital design engineer to integrate the low-speed peripheral subsystem I3C, I2C, SPI/QSPI/OSPI, UART controllers — including the IO cells, pad ring connectivity and IO multiplexing that these peripherals depend on.
Duties Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top Own IO-level integration: pad/IO cell selection and configuration, IO mux design and programmability, pull-up/pull-down, drive strength, open-drain vs. push-pull, bidirectional/tri-state control, retention and pad state during reset/power modes.
Develop glue and control logic: bus bridging (APB/AHB/AXI), register maps, clock and reset generation/gating, interrupt and DMA request routing, CDC Contribute to subsystem Architecture and top-level RTL; drive integration, verification plan development and verification support; apply Design-for-Verification concepts Extend and maintain our Python-based integration/generation tooling (IO mux tables, pinmux collateral, connectivity and register generation)
Support RTL-to-GDS: constraints, synthesis, timing closure, low-power (UPF) intent for the peripheral/IO domain Support FPGA prototyping, bring-up/validation, test program development and chip life to production maturity
Must Have
- 4+ years as a Digital Design Engineer, with SoC/subsystem integration ownership Hands-on integration of I3C, I2C, SPI/QSPI/OSPI and UART controllers
- Practical understanding of IOs/pads used for peripherals and of IO mux architecture and pinmux collateral
- Strong Verilog/SystemVerilog RTL coding; digital Architecture definition
- Python scripting — required, our integration tools are Python-based Tcl scripting; familiarity with synthesis and static timing
- Experience with UPF-based simulation/low-power flows SystemVerilog UVM/OVM exposure
- BS in Electrical/Computer Engineering or Computer Science, or equivalent experience
- Familiarity with AI assisted code
- IO system operations experience
Nice to Have
- CAN / CAN-FD protocol and CAN controller integration experience
- I3C advanced features (in-band interrupts, hot-join, dynamic address assignment, HDR modes)
- Sensor-hub or MCU subsystem integration; boot-from-flash (QSPI/OSPI, XIP) experience
- DFT/testability and test-program definition; Power-Aware GLS FPGA prototyping; PCIe/USB/MIPI exposure
- MSEE/CS Synopsys Core Consultant experience (IP configuration/generation and coreAssembler-based subsystem assembly)
Education
- Bachelors in Engineering required.
Note
- US - CA - Burlingame (Hybrid/Remote)