C Modelling Engineer - Remote / Telecommute

C Modelling Engineer - Remote / Telecommute

Posted 5 days ago by 1755240778

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Negotiable
Outside
Remote
USA
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Android (Operating System) Board Bring-Up C++ (Programming Language) Computer Architecture Computer Hardware Constructive Feedback Debugging Design Elements And Principles Device Drivers Embedded Operating Systems Ethernet Firmware Generic Programming Git (Version Control System) Management Memory Management Object-Oriented Design Object Oriented Modeling And Design Operating Systems Perl (Programming Language) Scheduling Serial Peripheral Interface Bus Software Development SystemC Systems Architecture Test Suite Universal Asynchronous Receiver/Transmitter USB Verification And Validation Version Control VxWorks

Summary: The SystemC Modelling Engineer will develop and maintain high-fidelity system-level models using SystemC for hardware/software co-design and verification. This role is essential for early performance analysis, architecture exploration, and functional validation of complex embedded systems. The engineer will collaborate with architecture, design, and verification teams to ensure model accuracy and efficiency, working on various platform components. The position requires a strong background in SystemC modeling and simulation of embedded systems.

Key Responsibilities:

  • Develop and maintain accurate and efficient SystemC models of platform components, including processors, memory controllers, and peripherals.
  • Implement TLM-based interfaces for communication between SystemC models and other simulation environments.
  • Validate the accuracy of SystemC models through comparison with RTL simulations and hardware prototypes, achieving a model fidelity target of X% (define target).
  • Collaborate with architecture and design teams to define modeling requirements and ensure models accurately reflect system specifications.
  • Contribute to the development of SystemC modeling guidelines and best practices within the organization.
  • Create and maintain documentation for SystemC models, including model descriptions, usage examples, and validation reports.
  • Debug and resolve issues identified during SystemC simulation, improving model performance and stability, reducing simulation time by X%.
  • Participate in code reviews and provide constructive feedback to other engineers.

Key Skills:

  • SystemC & TLM (Transaction Level Modeling).
  • C++ (Proficient level, including object-oriented design principles).
  • Hardware Description Languages (HDLs): VHDL or Verilog (Understanding and ability to interface with).
  • Simulation Tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Graphics QuestaSim).
  • Debugging Tools (e.g., GDB, DVE).
  • Scripting Languages (Python, Perl, or similar).
  • Version Control Systems (Git).
  • Embedded Systems Architecture (Understanding of processor architectures, memory hierarchies, and bus protocols).
  • Communication (Excellent written and verbal communication skills).
  • Problem-Solving (Strong analytical and problem-solving abilities).
  • Team Collaboration (Ability to work effectively in a team environment).
  • Defining transaction level models of non-memory mapped interfaces (I2C, SPI, USB, CAN, Ethernet etc).
  • Porting the embedded operating system (Linux, VXWorks, Android) on the virtual prototype, developing the device drivers etc.
  • Verification of models at IP & SoC level.
  • Develop regressable self-checking test suites using C/ARM assembly.
  • Develop System Level Flows and Methodologies using virtual prototypes.

Salary (Rate): £52.00 hourly

City: undetermined

Country: USA

Working Arrangements: remote

IR35 Status: outside IR35

Seniority Level: undetermined

Industry: IT

Detailed Description From Employer:
Job Description:
Pay Range: $60hr - $65hr
  • The SystemC Modelling Engineer will be responsible for developing and maintaining high-fidelity system-level models using SystemC for hardware/software co-design and verification.
  • This role is crucial for enabling early performance analysis, architecture exploration, and functional validation of complex embedded systems.
  • The engineer will work closely with architecture, design, and verification teams to ensure the accuracy and efficiency of the SystemC models.
  • Projects will involve modeling various components of a platform, including processors, memory subsystems, and peripherals.
  • The candidate will utilize SystemC, TLM (Transaction Level Modeling), and related simulation environments.
Requirement/Must Have:
  • SystemC & TLM (Transaction Level Modeling).
  • C++ (Proficient level, including object-oriented design principles).
  • Hardware Description Languages (HDLs): VHDL or Verilog (Understanding and ability to interface with).
  • Simulation Tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Graphics QuestaSim).
  • Debugging Tools (e.g., GDB, DVE).
  • Scripting Languages (Python, Perl, or similar).
  • Version Control Systems (Git).
  • Embedded Systems Architecture (Understanding of processor architectures, memory hierarchies, and bus protocols).
  • Communication (Excellent written and verbal communication skills).
  • Problem-Solving (Strong analytical and problem-solving abilities).
  • Team Collaboration (Ability to work effectively in a team environment).
  • Defining transaction level models of non-memory mapped interfaces (I2C, SPI, USB, CAN, Ethernet etc).
  • Porting the embedded operating system (Linux, VXWorks, Android) on the virtual prototype, developing the device drivers etc.
  • Verification of models at IP & SoC level.
  • Develop regressable self-checking test suites using C/ARM assembly.
  • Develop System Level Flows and Methodologies using virtual prototypes.
Experience:
  • 5+ years of experience in SystemC modeling and simulation of embedded systems.
  • Proven experience in developing and debugging SystemC models using industry-standard simulation tools.
Responsibilities:
  • Develop and maintain accurate and efficient SystemC models of platform components, including processors, memory controllers, and peripherals.
  • Implement TLM-based interfaces for communication between SystemC models and other simulation environments.
  • Validate the accuracy of SystemC models through comparison with RTL simulations and hardware prototypes, achieving a model fidelity target of X% (define target).
  • Collaborate with architecture and design teams to define modeling requirements and ensure models accurately reflect system specifications.
  • Contribute to the development of SystemC modeling guidelines and best practices within the organization.
  • Create and maintain documentation for SystemC models, including model descriptions, usage examples, and validation reports.
  • Debug and resolve issues identified during SystemC simulation, improving model performance and stability, reducing simulation time by X%.
  • Participate in code reviews and provide constructive feedback to other engineers.
Should Have:
  • Experience with Board bring-up, platform initialization, board support package development, peripherals such as PCIe, I2C, SPI, USB, UART, OS primitives, memory management, scheduling, interrupts, and multi-threading.
  • Good experience in system-level debugging with a comprehensive understanding of managing and prioritizing system-level issues.
  • Extensive background in firmware development or embedded software development within a multicore environment or hardware context.
Qualification And Education:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. Master's degree preferred.
  • Strong understanding of computer architecture principles and hardware/software co-design methodologies.
  • Excellent C++ programming skills and familiarity with object-oriented design principles.
  • Experience with TLM (Transaction Level Modeling) is highly desirable.
  • Familiarity with hardware description languages (VHDL or Verilog) is a plus.
  • Experience using Git for version control.
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