100% REMOTE::Design Verification Engineer ::ONLY W2

100% REMOTE::Design Verification Engineer ::ONLY W2

Posted Today by FutureTech Consultants LLC

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Negotiable
Undetermined
Remote
Remote
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Application Specific Integrated Circuits Code Coverage Computer Hardware Demand Flow Technology Digital Logic Firmware Formal Verification Git (Version Control System) Hardware Verification Language IBM WAS M (Programming Language) Management Microarchitecture Nice (Unix Utility) Perl (Programming Language) Python (Programming Language) Regression Testing Scripting Test Planning Verification And Validation

Summary: The Design Verification Engineer role at Appridat Solutions LLC involves verifying the functionality, performance, and robustness of custom silicon designs. The position requires collaboration with various engineering teams and emphasizes hands-on technical engagement. The role is fully remote but requires alignment with the PST time zone. Candidates should have a strong background in ASIC/SoC verification and relevant technical skills.

Key Responsibilities:

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.

Key Skills:

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git).

Salary (Rate): undetermined

City: undetermined

Country: undetermined

Working Arrangements: remote

IR35 Status: undetermined

Seniority Level: undetermined

Industry: Other

Detailed Description From Employer:

Hello,

Greetings.!

This is Hima from Appridat Solutions LLC. I was reviewing your resume online and would like to talk to you regarding an exciting opportunity for Design Verification Engineer We have with one of Appridat Solutions LLC premier clients.

Role Design Verification Engineer

Location - Remote (must be aligned with PST time zone)

Job Description and other details

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.

Responsibilities

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.

Qualifications

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git).

Nice to Have

  • Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
  • Familiarity with developing and integrating reference models.
  • Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI).
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus.

Regards,

Hima Bindu

Appridat solutions LLC.

5655 Peachtree Parkway, Suite 212, Peachtree Corners, GA 30092

PHONE:*533 | Fax

Direct:

Email:

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