Principal ASIC Verification Engineer (32625)

Summary: The Principal ASIC Verification Engineer will be responsible for developing verification infrastructure and executing test plans for advanced digital ASICs within a high-performing team focused on next-generation optical networks and data centers. The role involves collaboration with cross-functional teams and may include leading verification efforts for key deliverables. The position is hybrid, allowing for flexibility in work location. Candidates should possess extensive experience in ASIC verification, particularly with UVM and SystemVerilog.

Key Responsibilities:

• Drive the development of verification infrastructure using SystemVerilog and UVM.
• Create protocol/traffic generators, checkers, and testbenches aligned with functional and standards-based requirements.
• Define and implement test plans at the block and sub-chip levels for advanced digital ASICs.
• Develop and execute self-checking test environments to ensure thorough validation.
• Collaborate with cross-functional teams in a geographically distributed environment.
• Optionally lead small teams or verification efforts for key deliverables.

Key Skills:

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field (Master's preferred).
• 10+ years of experience in ASIC verification with hands-on expertise in UVM and SystemVerilog.
• Solid knowledge of assertions, functional and code coverage, and formal verification tools.
• Proficiency in scripting languages such as Python.
• Strong problem-solving skills and a collaborative mindset.
• Experience with DSP and/or FEC is a plus.

Salary (Rate): undetermined

City: undetermined

Country: USA

Working Arrangements: hybrid

IR35 Status: outside IR35

Seniority Level: undetermined

Industry: IT