Physical Design Engineer
Posted 2 weeks ago by European Tech Recruit
Negotiable
Inside
Hybrid
Cambridge, England, United Kingdom
Summary: The Physical Design Engineer role involves working with a leading semiconductor company in Cambridge on a 6-month PAYE contract, requiring 2 days onsite per week. The engineer will focus on RTL development and physical implementation of graphics processors, utilizing advanced techniques to enhance power, area, and frequency performance. Collaboration with EDA vendors and providing feedback to designers are key aspects of the position. The role is classified as inside IR35, indicating a requirement for compliance with tax regulations.
Key Responsibilities:
- Physical implementation of graphics processors from RTL through place and route to STA.
- Supplying RTL feedback to designers via Jira to improve PPA and remove implementation bottlenecks.
- Collaborating with EDA vendors to solve tool issues and advance PPA.
- Planning and scheduling of own work inline with the project goals and needs.
Key Skills:
- Experience with Cadence tools: Genus, Innovus, Tempus, QRC & Conformal.
- Proficiency in PnR Flow: Synthesis, LEC, CLP, Floorplan, Placement, CTS, PostCTS, Routing, STA.
- Familiarity with Synopsys tools: Fusion compiler, Formality.
- Knowledge of low power design techniques (power gating, DVFS, etc.).
- Understanding of building flows and methodology using scripting languages such as TCL, Python, Perl.
Salary (Rate): undetermined
City: Cambridge
Country: United Kingdom
Working Arrangements: hybrid
IR35 Status: inside IR35
Seniority Level: undetermined
Industry: IT
Physical Design Engineer
European Tech Recruit are working closely with a leading semicon company, based in Cambridge, who are looking for a talented Physical Design Engineer to join their team . This will be an initial 6 month PAYE contract (inside IR35) with strong likelihood of further extensions. 2 days onsite p/w required in Cambridge. In this role you will influence RTL development for best-in-class PPA whilst innovating, crafting, and deploying the latest implementation techniques on live projects pushing the boundaries of power, area and frequency.
Responsibilities as Physical Design Engineer:
- Physical implementation of graphics processors using the entire implementation flow from RTL through place and route to STA.
- Supplying RTL feedback to designers via Jira to improve PPA and remove implementation bottlenecks.
- Collaborating with EDA vendors to solve tool issues and advance PPA.
- Planning and scheduling of own work inline with the project goals and needs.
Requirements:
- Cadence: Genus, Innovus, Tempus, QRC & Conformal.
- PnR Flow: Synthesis, LEC, CLP, Floorplan, Placement, CTS, PostCTS, Routing, STA.
- Synopsys: Fusion compiler, Formality. Synthesis, LEC.
- Low power design techniques (power gating, DVFS etc.).
- Understanding in building flows and methodology using scripting languages such as TCL, Python, Perl to support project development.
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