Design Verification Engineer
Posted 2 weeks ago by Clarion Chase
Negotiable
Undetermined
Undetermined
United Kingdom
Summary: The role of Design Verification Engineer involves working with a semiconductor design house on a critical customer project, requiring a minimum of 10 years of experience in digital design and UVM. The contract is expected to last at least 5 months, focusing on various essential technical areas such as power management and cache coherence. Candidates must have a strong background in design verification and related technologies. Insufficient information provided in the job description.
Key Responsibilities:
- Engage in design verification for semiconductor projects.
- Utilize UVM for verification processes.
- Work on boot, clocking, and reset management.
- Develop power management solutions and UPF.
- Handle cache coherence and mesh networks.
- Manage DDR and PCIe/Die-to-Die interfaces.
Key Skills:
- 10+ years of experience in design verification.
- Digital design background.
- Proficiency in UVM.
- Experience with boot, clocking, and reset management.
- Power management and UPF development experience.
- Knowledge of cache coherence and mesh networks.
- Familiarity with DDR and PCIe/Die-to-Die technologies.
Salary (Rate): undetermined
City: undetermined
Country: United Kingdom
Working Arrangements: undetermined
IR35 Status: undetermined
Seniority Level: undetermined
Industry: Other
We are representing a semiconductor design house in urgent need of a Design Verification Engineer for a business-critical customer project. The contract length will be a minimum of 5 months. 10+ years of experience in a similar role Digital design background UVM experience is key Experience with one or several of these is essential: Boot, clocking and reset management experience Power Management (and UPF development) experience Cache coherence / Mesh Networks DDR PCIe/Die-to-Die