Design Verification Engineer

Summary: The Design Verification Engineer is responsible for creating and implementing a coverage-driven verification plan, developing a UVM verification environment, and ensuring CPU connectivity to IP blocks. The role involves writing test plans, developing test benches, and completing functional verification for design blocks in SoCs/Subsystems. Additionally, the engineer will run regressions, debug failures, and provide verification reports to demonstrate test success on the RTL.

Key Responsibilities:

• Create coverage driven verification plan document.
• Create UVM verification environment.
• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain).
• Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification and close coverage for all agreed design blocks in the SoCs/Subsystems.
• Run regressions, debug test failures and file bug reports as needed.
• Develop tests to meet functional coverage and code coverage requirements based on analysis of coverage gaps.
• Provide verification report as needed to show all implemented tests passing on the RTL.
• Utilize a mix of design checks and verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases.

Key Skills:

• Experience with UVM verification environment.
• Proficiency in Verilog/System Verilog.
• Knowledge of CPU connectivity verification techniques.
• Ability to write test plans and develop test benches.
• Experience in running regressions and debugging test failures.
• Understanding of functional and code coverage requirements.
• Familiarity with simulators and emulators.

Salary (Rate): undetermined

City: undetermined

Country: United Kingdom

Working Arrangements: undetermined

IR35 Status: undetermined

Seniority Level: undetermined

Industry: IT