RTL Design Engineer Wireless SoC
Posted 1 week ago by FutureTech Consultants LLC
Negotiable
Undetermined
Remote
Remote
Summary: The RTL Design Engineer for Wireless SoC will focus on the design and implementation of high-performance digital blocks for next-generation wireless systems. This remote position requires collaboration with various teams to ensure the delivery of production-quality silicon while working within the PST time zone. The ideal candidate will have extensive experience in RTL design and DSP hardware implementation. Key responsibilities include translating specifications into synthesizable RTL and optimizing power, performance, and area (PPA) metrics.
Key Responsibilities:
- Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog/Verilog
- Translate architectural and algorithmic specifications into synthesizable RTL
- Implement DSP blocks such as filtering, FFT/IFFT, beamforming, etc.
- Develop RTL for SoC components including interfaces, clock/reset, power management, and debug logic
- Work with internal and external IP integration into chip-level designs
- Collaborate with AMS teams on digital-analog interfaces, calibration logic, and control systems
- Drive PPA (power, performance, area) optimization and support timing closure with backend teams
- Participate in design reviews, integration, synthesis, and timing closure activities
- Support silicon bring-up and lab validation of digital subsystems
Key Skills:
- 5+ years of hands-on RTL design experience (SystemVerilog / Verilog)
- Strong understanding of micro-architecture and RTL implementation from specs
- Experience in DSP hardware implementation (filtering, FFT, etc.)
- Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
- Experience with synthesis, linting, simulation, and STA tools
- Understanding of DFT concepts (scan, BIST)
- Strong debugging and problem-solving skills
- Good communication and ability to work in cross-functional teams
Salary (Rate): undetermined
City: undetermined
Country: undetermined
Working Arrangements: remote
IR35 Status: undetermined
Seniority Level: undetermined
Industry: IT
RTL Design Engineer Wireless SoC
Location: Remote (must be aligned with PST time zone / willing to work PST hours)
Long term We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon. Key Responsibilities
Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog/Verilog
Translate architectural and algorithmic specifications into synthesizable RTL
Implement DSP blocks such as filtering, FFT/IFFT, beamforming, etc.
Develop RTL for SoC components including interfaces, clock/reset, power management, and debug logic
Work with internal and external IP integration into chip-level designs
Collaborate with AMS teams on digital-analog interfaces, calibration logic, and control systems
Drive PPA (power, performance, area) optimization and support timing closure with backend teams
Participate in design reviews, integration, synthesis, and timing closure activities
Support silicon bring-up and lab validation of digital subsystems Required Skills
5+ years of hands-on RTL design experience (SystemVerilog / Verilog)
Strong understanding of micro-architecture and RTL implementation from specs
Experience in DSP hardware implementation (filtering, FFT, etc.)
Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
Experience with synthesis, linting, simulation, and STA tools
Understanding of DFT concepts (scan, BIST)
Strong debugging and problem-solving skills
Good communication and ability to work in cross-functional teams